Nonvolatile memory apparatuses are widely used to be built into a variety of portable hardware such as cellular phones and digital cameras, and their uses have been spreading at a high pace. In recent years, in many occasions, audio data or image data have been used, and hence there has been a strong demand for nonvolatile memory apparatuses which have a larger capacity and are operable at a higher speed. Besides, in fields of nonvolatile memory apparatuses for use with portable hardware, there has been a further demand for lower electric power consumption.
At present, a major nonvolatile memory apparatus is a flash memory. The flash memory is adapted to store data by controlling electric charges accumulated on a floating gate. It is pointed out that the flash memory has a problem that, since the flash memory has a structure in which the electric charges are accumulated in a high electric field on the floating gate, there is a limitation in reduction of its size and it is difficult to achieve miniaturization which is required to achieve a larger capacity. In addition, in the flash memory, specified blocks must be erased all at once without fail to rewrite data, and a programming time is long. Because of such properties, in the flash memory, a very long time is needed to rewrite data and there is a limitation in an increase in a speed.
As a nonvolatile memory apparatus in next generation which can solve these problems, there is a nonvolatile memory apparatus using a resistance variable element which is adapted to store data according to a change in its electric resistance. As the nonvolatile memory using a resistance variable element which is currently proposed, there are MRAM (Magnetic RAM), PRAM (Phase-Change RAM), ReRAM (Resistive RAM), etc.
Patent document 1 discloses an example of a control method of a ReRAM element using an oxide having a perovskite structure. Hereinafter, the control method of the ReRAM element will be described with reference to the drawings.
FIGS. 25 to 27 are views showing the control method of memory cells disclosed in Patent document 1. A memory cell 19 includes a resistance variable element 11 and a selection transistor 12. One terminal of the resistance variable element 11 and one main terminal (drain or source) of the selection transistor 12 are connected to each other. The other main terminal (source or drain) of the selection transistor 12 is connected to a source line terminal 13 by a source line 16. The other terminal of the resistance variable element 11 is connected to a bit line terminal 15 by a bit line 18. The gate of the selection transistor 12 is connected to a word line terminal 14 by a word line 17. In any cases where data is written (“1” is written), data is erased (“0” is written), and data is read, an ON-voltage at a high level is applied to the word line terminal 14 of the selected memory cell, causing the selection transistor 12 to be placed in an electrically-conductive state.
FIG. 25 is a view showing a state where an electric pulse is applied when a write operation is performed in the memory cell of Patent document 1. The source line 16 is set to 0V (electrically grounded). A positive write pulse having a predetermined write voltage amplitude is applied to the bit line 18 and desired data is written to the resistance variable element 11. In a case where multi-valued data is written to the resistance variable element 11, the voltage amplitude of the write pulse is set to a level according to the value of data to be written. For example, in a case where four-valued data is written to one resistance variable element 11, one voltage amplitude is selected from among specified four voltage amplitudes determined according to the respective values of the write data and a write operation is performed. As a write pulse width, a proper width according to the element is selected. That is, to switch the element to a predetermined resistance state, there exist one voltage amplitude level and one pulse width corresponding to the predetermined resistance state.
FIG. 26 is a view showing a state where an electric pulse is applied when an erase operation is performed in the memory cell of Patent document 1. The bit line is set to 0V (electrically grounded), and the source line is applied with a positive erase pulse having a predetermined erase voltage amplitude. In response to the erase pulse applied, the electric resistance of the resistance variable element 11 is caused to have a minimum value. Patent document 1 discloses that when the erase pulse is applied to a specified source line with plural bit lines set to 0V, plural memory cells connected to the plural bit lines and to the source line are erased simultaneously all at once.
FIG. 27 is a view showing a state where an electric pulse is applied when a read operation is performed in the memory cell of Patent document 1. When data stored in the resistance variable element 11 is read, the source line 16 is set to 0V (electrically grounded) and a predetermined read voltage is applied to the selected bit line 18 via a read circuit. Upon the application of the read voltage, a comparator/determiner circuit compares a level of the bit line 18 to a reference level for read, so that the stored data is read.
Non-Patent document 1 discloses a ReRAM element which is switched between the high-resistance state and the low-resistance state in response to applied electric pulses which are identical in polarity and different in voltage and pulse width. In the ReRAM element of Non-Patent document 1, TMO (transition metal oxide) is used as the resistance variable material. The ReRAM element is switchable to the high-resistance state and to the low-resistance state in response to electric pulses which are identical in polarity. FIG. 28 is a view showing a voltage-current characteristic of the ReRAM element of Non-Patent document 1. As shown in FIG. 28, in “SET” in which the ReRAM element is switched from the high-resistance state to the low-resistance state, a more current than before flows when the element has been switched from the high-resistance state to the low-resistance state unless a set current compliance is used. In this case, the ReRAM element is switched again from the low-resistance state to the high-resistance state unexpectedly (incorrect operation), or the element may be broken down due to an excess current. Therefore, it is necessary to use a set current compliance at a predetermined first current value. In “RESET” in which the ReRAM element is switched from the low-resistance state to the high-resistance state, a current is flowed in the ReRAM element at a second current value which is not smaller than the first current value. Unless the absolute value of the voltage applied to the both ends of the resistance variable element is restricted to a value smaller than a certain value after the element has been switched from the low-resistance state to the high-resistance state, an incorrect operation occurs, for example, the resistance state of the element is switched again from the high-resistance state to the low-resistance state unexpectedly.
As described above, for the ReRAM element which is switched to the high-resistance state and to the low-resistance state in response to the applied voltages which are identical in polarity, it is necessary to control a driver circuit for causing the switching of the resistance state so that the first current value or the second current value is selectively used, according to the resistance state of the element. In addition, it is necessary to restrict the voltage applied to the resistance variable element as desired, in the driver circuit.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2004-185756    Non-Patent document 1: Baek, J. G. et al., 2004, “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, TEDM Technical Digest pp. 587-590